MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, instead of silicon dioxide, can reduce gate leakage. Because, however, such a dielectric may not be compatible with polysilicon, it may be desirable to use metal gate electrodes in devices that include high-k gate dielectrics.
When making a CMOS device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a first trench between the spacers. A first workfunction metal is deposited within the trench. A second polysilicon layer is then removed to create a second trench, and replaced with a second workfunction metal that differs from the first workfunction metal.
When applying such a replacement gate process, it may be advantageous to fill only part of the trenches with the workfunction metals, then fill the remainder of the trenches with a fill metal. In the resulting structure, the high-k gate dielectric layer, upon which the metal layers are formed, may spill over onto an oxide layer that separates the trenches. Similarly, part of the workfunction and fill metals may form above that oxide layer. In current processes, a polishing operation, e.g., a chemical mechanical polishing (“CMP”) step, may be applied to remove the high-k gate dielectric layer, the workfunction metal, and the fill metal from above the oxide layer.
If the workfunction metals polish slowly, it may require a relatively long overpolish step to completely remove them. When such an overpolish step is not selective to the underlying high-k gate dielectric layer, significant lot to lot or wafer to wafer variation in the thickness of an underlying oxide layer may result. In some cases, severe reduction in oxide thickness may occur over parts of a wafer by the time the polishing operation is completed.
Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric layer and a metal gate electrode. There is a need for such a process that enables removal of fill and workfunction metals from above an underlying dielectric layer (e.g., an oxide layer) without removing significant portions of that underlying layer and without causing the dielectric layer to manifest significant variation in thickness. The method of the present invention provides such a process.
Features shown in these figures are not intended to be drawn to scale.